Registers

reg0: receives immediate numbers

reg1: left operand of ALU

reg2: right operand of ALU

reg3: result of ALU, judging number of COND

reg4, reg5: simply stores data

Instruction Set Architecture

(In fact, these macros must be set by yourself.)

Imm instructions

1-63: immediate numbers

ALU instructions

64: or

65: nand

66: nor

67: and

68: add

69: sub

70-127: undefined

Copy instructions

128: 0 -> 0

129: 0 -> 1

130: 0 -> 2

131: 0 -> 3

132: 0 -> 4

133: 0 -> 5

134: 0 -> out

135: undefined

Absolutely same as above:

136-143: from 1 -> 0 to undefined

144-151: from 2 -> 0 to undefined

152-159: from 3 -> 0 to undefined

160-167: from 4 -> 0 to undefined

168-175: from 5 -> 0 to undefined

176-183: from in -> 0 to undefined

184-191: undefined

Conditional Branches

192: never

193: = 0

194: < 0

195 <= 0

196 always

197 != 0

198 >= 0

199 > 0

This is your HOMIE number 43, I ain’t dead.

This is your best lever-presser VictorZhangAI (as VictorZhang was signed in by someone else int64_t ago) a.k.a VZstless.

A water floatingnologist and a fish ruaaningnologist, as well as a class escapist from HITWH.

A discussing member of chive and a main contributor of HITWH-CS (mainly the Rui-Qi parts).

A fan of old software and hardware, also a fan of cold side of Computer Technology.

A retired web front-end maker.